During integrated circuit (IC) fabrication, many device layers (e.g., metal layers, dielectric layers, silicon layers, etc.) are often disposed upon and/or proximate one another. These layers may include a plurality of components and may be interconnected to form the IC. Some components, layers, and designs may include the use and/or inclusion of thick (e.g., about 3 μm to about 10 μm) wires. These thick wires may include copper and can be disposed proximate aluminum components/layers in the IC, forming components such as interconnects, portions of inductors, etc. For example, in ICs designed to be used as a part of radio-frequency (RF) technology, thick copper wires are often utilized to produce inductors with a quality factor (e.g., the ratio of inductive reactance to resistance at a given frequency) which meets design specifications.
In such structures, a capping or passivation layer may be disposed over the copper wires, which forms a hermetic seal over the copper wire. These passivation layers may be, for example, SiN layers deposited using conventional plasma enhanced chemical vapor deposition (PECVD) processes. These passivation layers are then covered with a polyimide material (dielectric layer). However, there is a large mismatch in coefficient of thermal expansion (CTE) between the copper, the passivation layers (e.g., SiN) and the dielectric layers. This large CTE mismatch can, in turn, cause cracks in the dielectric layers.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.